* Separate independent read and write data ports
* Supports concurrent transactions
* 550-MHz clock for high bandwidth
* Four-word burst for reducing add.

144-Mbit QDR II+ SRAM Four-Word Burst Architecture

+

CY7C266

CY7C2665KV18

CY7C261

CY7C263

CY7C264

CY7C2642KV18

CY7C2644KV18

CY7C265

CY7C2670KV18

CY7C2163KV18

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